Yield Reliability Engineering in Semiconductor Manufacturing: Quantitative Control of Defectivity, Overlay, and Linewidth Under Process Drift

Abstract

This article presents a quantitative yield reliability framework that models yield loss as a consequence of uncertainty propagation through process control loops, linking defectivity, overlay, and linewidth control to operational decisions such as tool matching, run-to-run control tuning, and lot disposition. The proposed approach integrates metrology uncertainty characterization, process drift modeling, multivariate statistical process control, and risk-based hold and release governance, with performance evaluated using probability of excursion detection, false alarm burden, time-to-decision, and expected yield at risk. A generic case-based analysis is developed for a representative lithography-etch stack where overlay and critical dimension interact with defectivity, demonstrating how random variation and systematic drift generate different failure signatures and require different control actions. Results indicate that the largest operational gains come from governance rather than from aggressive thresholding, specifically by combining stage-aware baselines, persistence rules, and verification pathways that separate true drift from transient noise and measurement bias, and by prioritizing control actions based on yield-risk impact rather than on deviation magnitude alone. The paper provides copy-ready tables and figure prompts suitable for Techne submission and for manufacturing reporting, and concludes with practical guidance for implementing yield reliability engineering as a decision system that balances sensitivity, stability, and throughput.