Semiconductor Wafer Fab Yield: Quantifying Defect Escape, Metrology Uncertainty, and Time-to-Containment Under Process Drift and Inspection Capacity Constraints

Abstract

This article presents an engineering-oriented reliability framework for wafer fab yield management that models end-to-end uncertainty propagation from process drift and measurement uncertainty through sampling-based inspection, excursion detection, and containment decisions into distributional outcomes relevant to manufacturing performance, including probability of defect escape, expected affected wafers before containment, false containment probability, time-to-detection and time-to-containment distributions, and an economic yield-loss index. A scenario-based quantitative study is developed for a generic high-volume fab with multiple critical tools and a mix of in-line metrology and inspection, comparing four architectures: baseline control charts with fixed sampling, expanded inspection without governance, model-based excursion detection with limited capacity awareness, and a governance-optimized two-tier architecture that combines drift-aware metrology validation, dynamic sampling allocation based on risk and tool health, staged containment policies, and capacity-aware triage for engineering review. Results show that increasing inspection without governance can reduce defect escape but can increase false containment and cycle-time penalties, that model-based detection improves time-to-detection but can fail under miscalibration and review overload, and that a two-tier governed approach reduces expected yield loss by reducing tail propagation and stabilizing containment decisions under drift and capacity constraints. Three copy-ready tables and complete prompts for data-driven figures are provided for Techne submission.